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d a t a sh eet preliminary speci?cation file under integrated circuits, ic01 1996 jun 19 integrated circuits saa7385 error correction and host interface ic for cd-rom (sequoia)
1996 jun 19 2 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (sequoia) saa7385 contents 1 features 1.1 general 1.2 53cf94 scsi controller 1.3 80c32 high-speed microcontroller 1.4 front-end interface logic 1.5 buffer controller 1.6 hardware third-level error correction 1.7 additional product support 2 general description 3 quick reference data 4 ordering information 5 block diagram 6 pinning 7 functional description 7.1 80c32 microcontroller 7.2 53cf94 fast scsi controller 7.3 input clock doubler 7.4 front-end 8 microcontroller interface 8.1 microcontroller interface status register 8.2 microcontroller interface command register 8.3 microcontroller interrupts 8.4 microcontroller ram organization 9 front panel and miscellaneous control signals 9.1 s2b uart registers 9.2 miscellaneous control registers 10 front-end 10.1 minute second frame (msf) addressing and header information 10.2 front-end status and control 11 buffer manager 11.1 front-end to buffer manager interface 11.2 microcontroller to buffer manager interface 11.3 ecc to buffer manager interface 11.4 scsi to buffer manager interface 11.5 miscellaneous buffer manager considerations 11.6 53cf94 related registers 12 frame buffer organization 13 summary of control register map 14 limiting values 15 operating characteristics 15.1 i 2 s-bus timing; data mode 15.2 eiaj timing; audio mode 15.3 r-w timing (see fig.15) 15.4 c-flag timing (see fig.16) 15.5 s2b interface timing 15.6 scsi interface timing 15.7 microprocessor interface 15.8 dram interface (the saa7385 is designed to operate with standard 70 ns drams) 16 package outline 17 soldering 17.1 introduction 17.2 reflow soldering 17.3 wave soldering 17.4 repairing soldered joints 18 definitions 19 life support applications
1996 jun 19 3 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (sequoia) saa7385 1 features 1.1 general single chip digital solution for an 8 speed cd-rom controller chip 10 mbytes/s ncr53cf94 equivalent scsi controller included high-speed 80c32 microcontroller with 256 8 scratch-pad sram included high performance cd-rom interface logic 128 pin qfp package. 1.2 53cf94 scsi controller separate clock input to allow operation up to the maximum 10 mbytes/s fast synchronous scsi-2 compatible 24-bit transfer counter for single transfers up to 16 mbytes high-speed 16-bit dma interface to the buffer manager dram on-chip 48 ma scsi drivers software compatible with members of the 53c90 family allows for scam support. 1.3 80c32 high-speed microcontroller 33.87 mhz full system speed operation three timers/event counters programmable full duplex serial channel eight general purpose microcontroller i/o pins external program rom. 1.4 front-end interface logic full 8 speed hardware operation block decoder sector sequencer crc checking of mode 1 and mode 2, form 1 sectors 212 ms watch-dog timer sub-code interface with synchronization c-flag interface for absolute time stamp. 1.5 buffer controller ten level arbitration logic utilizes low cost 70 ns drams page mode dram access for high-speed error correction and scsi data transfer data organization by 3 kbyte frames 256 kbyte or 1 mbyte dram supported. 1.6 hardware third-level error correction third-level correction provides superior performance in unfavourable conditions full hardware error correction to reduce microcontroller overhead corrections are automatically written to the dram frame buffer. 1.7 additional product support all control registers mapped into 80c32 special function memory space dedicated s2b interface uart input clock synthesizer red book audio pass through. 2 general description the saa7385 is a high integration asic that incorporates all of the digital electronics necessary to connect a cd decoder to a scsi host. an 80c32 microcontroller and a 53cf94 scsi controller are embedded in the asic. the following functions are supported: input clock doubler block decoder crc checking of mode 1 and mode 2, form 1 sectors red book audio pass through to scsi buffer manager third-level error correction sub-code and q-channel support dedicated s2b interface uart embedded 80c32 microcontroller embedded 53cf94 scsi controller.
1996 jun 19 4 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (sequoia) saa7385 the saa7385 uses a 33.8688 mhz clock and is capable of accepting data at eight times (n = 8 or 1.4 mbytes/s) the normal cd-rom data rate. third level error correction hardware is included to improve the correction efficiency of the system. the buffer manager hardware utilizes a ten-level arbitration unit and can stop the clock to the microcontroller to emulate a wait condition when necessary. the saa7385 comprises five major functional blocks: the 80c32 microcontroller is an industry standard core the 53cf94 is an industry standard core the front-end block connects to the external cd-60 based decoder and fully processes the incoming data stream to provide bytes of data that are stored in the external buffer the buffer manager block provides the address generation and timing control for the external dram buffer the ecc block performs the error correction functions in hardware on the data in the dram buffer. supply of this compact disc ic does not convey an implied license under any patent right to use this ic in any compact disc application. 3 quick reference data 4 ordering information symbol parameter min. typ. max. unit v dd digital supply voltage 4.5 5.0 5.5 v t amb operating ambient temperature 0 - 70 c t stg storage temperature - 55 - +150 c type number package name description version SAA7385GP sqfp128 plastic quad ?at package; 128 leads (lead length 1.6 mm); body 14 20 2.8 mm sot387-2
1996 jun 19 5 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (sequoia) saa7385 5 block diagram 6 pinning all input, output and bidirectional signals are ttl level unless otherwise stated (pull-down = pd25 = 25 m a; pull-up = pu25 = 25 m a, pu400 = 400 m a; slew = s2 = 2 ma, s4 = 4 ma; cmos slew = cmos s2 = cmos 2 = 2 ma; scsi pad = scsi = 48 ma). symbol pin i/o pad description da2 1 o s4 dram address bus; bit da2 da3 2 o s4 dram address bus; bit da3 da4 3 o s4 dram address bus; bit da4 v ss1 4 -- ground 1 da5 5 o s4 dram address bus; bit da5 da6 6 o s4 dram address bus; bit da6 da7 7 o s4 dram address bus; bit da7 da8 8 o s4 dram address bus; bit da8 da9 9 o s4 dram address bus; bit da9 v dd1 10 -- power supply 1 fig.1 block diagram (simplified). handbook, full pagewidth mge388 data converter and sub-code uart layered error corrector buffer mapper 53cf94 scsi buffer manager data subcode microcontroller interface debug uart 80c32 microcontroller cd decoder servo processor data saa7385 subcode c-flag 64k 8 rom 256k 8 or 1m 8 dram buffer scsi interface debug uart s2b serial interface
1996 jun 19 6 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (sequoia) saa7385 ras 11 o s4 dram row address section; active low cas 12 o s4 dram column address selection; active low dwr 13 o s4 dram write; active low doe 14 o s4 dram output enable; active low v ss2 15 -- ground 2 dd0 16 i/o 4 ma, schmitt, pd25 dram data bus; bit dd0 dd1 17 i/o 4 ma, schmitt, pd25 dram data bus; bit dd1 dd2 18 i/o 4 ma, schmitt, pd25 dram data bus; bit dd2 dd3 19 i/o 4 ma, schmitt, pd25 dram data bus; bit dd3 v dd2 20 -- power supply 2 dd4 21 i/o 4 ma, schmitt, pd25 dram data bus; bit dd4 dd5 22 i/o 4 ma, schmitt, pd25 dram data bus; bit dd5 dd6 23 i/o 4 ma, schmitt, pd25 dram data bus; bit dd6 dd7 24 i/o 4 ma, schmitt, pd25 dram data bus; bit dd7 v ss3 25 -- ground 3 led 26 o 24 ma, cmos test panel led; active low; wtgctl(4) tra ysw 27 i schmitt, pu25 active low when tray is in eject 28 i schmitt, pu25 opens tray; active low lqdata 29 o 2 ma serial data to dac lwclk 30 o 2 ma word strobe to dac v ss4 31 -- ground 4 sclk 32 o 2 ma data serial clock v ss5 33 -- ground 5 sysres 34 o 2 ma, pu25 system reset; or of por, scsirst and watch-dog timer cflag 35 i schmitt, pu400 c1 and c2 status cpr 36 o 2 ma s2b interface ready to accept data; active low spr 37 i schmitt s2b interface ready to send data; active low skipfwd 38 i schmitt, pu25 skip forwards; active low; rdsw(3) skipback 39 i schmitt, pu25 skip backwards; active low; rdsw(2) scsiclk 40 i standard scsi interface clock v dd3 41 -- power supply 3 ad0 42 i/o s4, schmitt microcontroller multiplexed data bus; bit ad0 ad1 43 i/o s4, schmitt microcontroller multiplexed data bus; bit ad1 ad2 44 i/o s4, schmitt microcontroller multiplexed data bus; bit ad2 ad3 45 i/o s4, schmitt microcontroller multiplexed data bus; bit ad3 ad4 46 i/o s4, schmitt microcontroller multiplexed data bus; bit ad4 ad5 47 i/o s4, schmitt microcontroller multiplexed data bus; bit ad5 ad6 48 i/o s4, schmitt microcontroller multiplexed data bus; bit ad6 ad7 49 i/o s4, schmitt microcontroller multiplexed data bus; bit ad7 v ss6 50 -- ground 6 la0 51 o cmos s2, pu25 eprom latched lower address; bit la0 symbol pin i/o pad description
1996 jun 19 7 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (sequoia) saa7385 la1 52 o cmos s2, pu25 eprom latched lower address; bit la1 la2 53 o cmos s2, pu25 eprom latched lower address; bit la2 la3 54 o cmos s2, pu25 eprom latched lower address; bit la3 v dd4 55 -- power supply 4 la4 56 o cmos s2, pu25 eprom latched lower address; bit la4 la5 57 o cmos s2, pu25 eprom latched lower address; bit la5 la6 58 o cmos s2, pu25 eprom latched lower address; bit la6 la7 59 o cmos s2, pu25 eprom latched lower address; bit la7 v ss7 60 -- ground 7 a8 61 o cmos s2, pu25 eprom upper address; bit a8 a9 62 o cmos s2, pu25 eprom upper address; bit a9 a10 63 o cmos s2, pu25 eprom upper address; bit a10 a11 64 o cmos s2, pu25 eprom upper address; bit a11 a12 65 o cmos s2, pu25 eprom upper address; bit a12 a13 66 o cmos s2, pu25 eprom upper address; bit a13 a14 67 o cmos s2, pu25 eprom upper address; bit a14 a15 68 o cmos s2, pu25 eprom upper address; bit a15 psen 69 o cmos 2, pu25 program store enable; active low v ss8 70 -- ground 8 io 71 i/o scsi scsi phase signal, active low req 72 i/o scsi scsi request, active low cd 73 i/o scsi scsi phase signal, active low sel 74 i/o scsi scsi select, active low v ss9 75 -- ground 9 msg 76 i/o scsi scsi phase signal, active low ack 77 i/o scsi scsi acknowledge, active low bsy 78 i/o scsi scsi busy, active low v ss10 79 -- ground 10 a tn 80 i/o scsi output in initiator mode; input in target mode, active low v dd5 81 -- power supply 5 sdp 82 i/o scsi scsi parity, active low sd7 83 i/o scsi scsi data bus; bit sd7 sd6 84 i/o scsi scsi data bus; bit sd6 sd5 85 i/o scsi scsi data bus; bit sd5 v ss11 86 -- ground 11 sd4 87 i/o scsi scsi data bus; bit sd4 sd3 88 i/o scsi scsi data bus; bit sd3 sd2 89 i/o scsi scsi data bus; bit sd2 sd1 90 i/o scsi scsi data bus; bit sd1 sd0 91 i/o scsi scsi data bus; bit sd0 v ss12 92 -- ground 12 symbol pin i/o pad description
1996 jun 19 8 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (sequoia) saa7385 rxs2b 93 i schmitt, pu25 s2b interface receive txs2b 94 o 4 ma s2b interface transmit tra yin 95 i/o 4 ma, pd25 tray extend control; active low (general purpose signal) tra yout 96 i/o 4 ma, pd25 tray retract control; active low (general purpose signal) scsirst 97 i schmitt scsi reset, active low; also causes a system reset por 98 i cmos power-on reset; active low v dd6 99 -- power supply 6 uc_port1.7 100 i/o cmos 2, pu25 drive speed select; microcontroller port 1.7 rab_musb 101 i/o cmos 2, pu25 rd/wr, acknowledge; microcontroller port 1.2 nrst_seq 102 i/o cmos 2, pu25 reset to engine; microcontroller port 1.5 uc_port1.4 103 i/o cmos 2, pu25 general purpose microcontroller i/o port; port 1.4 uc_port1.3 104 i/o cmos 2, pu25 general purpose microcontroller i/o port; port 1.3 uc_port1.1 105 i/o cmos 2, pu25 general purpose microcontroller i/o port; port 1.1 homesw 106 i/o 2 ma, pu25 actuator sled home; active low; microcontroller port 1.0 pla y 107 i schmitt laser on and focused status; active low; rdsw(4) uc_port1.6 108 i/o cmos 2, pu25 general purpose microcontroller i/o port; port 1.6 v ss13 109 -- ground 13 gpi1 110 i schmitt, pu25 general purpose input; microcontroller port 3.4 gpi2 111 i schmitt, pu25 general purpose input; microcontroller port 3.5 kill 112 i schmitt, pu25 shut off audio; active low txice 113 o 4 ma debug uart output; from 80c32 serial port rxice 114 i schmitt, pu25 debug uart input; to 80c32 serial port rxsub 115 i schmitt, pu25 sub-code input v dd7 116 -- power supply 7 oscin 117 i standard master input clock; 34 or 16 mhz v ss14 118 -- ground 14 clab 119 i schmitt clock v ss15 120 -- ground 15 daab 121 i schmitt data wsab 122 i schmitt word strobe efab 123 i schmitt error ?ag clk34 124 o 2 ma 34 mhz output clock test 125 i schmitt, pd25 test pin; must be ground v ss16 126 -- ground 16 da0 127 o s4 dram address bus; bit da0 da1 128 o s4 dram address bus; bit da1 symbol pin i/o pad description
1996 jun 19 9 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (sequoia) saa7385 fig.2 pin configuration. handbook, full pagewidth 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 59 60 61 62 63 64 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 30 29 28 27 26 25 24 23 22 21 20 38 37 36 35 34 33 32 31 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 mge387 saa7385 dd1 dd2 dd3 v dd2 dd4 dd5 dd6 dd7 v ss3 lqdata lwclk v ss4 sclk da2 da3 da4 v ss1 da5 da6 da7 da8 da9 v dd1 v ss2 dd0 ras cas doe dwr led traysw eject v ss5 sysres cflag skipfwd cpr spr scsiclk v dd3 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 v ss6 la0 la1 la2 la3 v dd4 la4 la5 la6 la7 v ss7 a8 a9 a10 a11 skipback atn v ss10 bsy ack msg v ss9 v ss8 a15 a14 a13 a12 trayout trayin txs2b rxs2b v ss12 sd0 sd1 sd2 sd3 sd4 v ss11 sd5 sd6 sd7 sdp v dd5 psen req io cd sel nrst_seq rab_musb uc_port1.7 v dd6 scsirst por da1 da0 v ss16 test clk34 efab wsab daab v ss15 clab v ss14 oscin v dd7 rxsub rxice txice gpi2 gpi1 v ss13 uc_port1.6 uc_port1.1 uc_port1.3 uc_port1.4 homesw kill play
1996 jun 19 10 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (sequoia) saa7385 n dbook, full pagewidth cdm 12.6 3-beam mechanism diode amplifier laser supply oq8866 laser on off track laser drive sledge home switch hf signal sledge drive single/double/ quadruple speed radial servo focus servo motor drive loader in loader out loader status focus and radial data digital servo control oq8868 cd decoder lo9585 servo control micro cdt663 om5234/fbx cd loader en xtal reset data clock scsi block decoder interface SAA7385GP + 256k/1m dram dac tda1305 audio processor tda1308 i 2 s i 2 s s2b q to w 64k (p)rom cdt665 right output left output scsi-2 interface with fast synchronous and scam digital servo drivers oq8844 + tda7072a(t) l1266 mge389 fig.3 example of cd-rom system with scsi-2 interface.
1996 jun 19 11 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (sequoia) saa7385 7 functional description 7.1 80c32 microcontroller the standard specification for details of the operation for this part may be found in any data sheet covering the 80c32 microcontroller. the one deviation from a normal 80c32 is the addition of all of the control registers for the special function register map for the 80c32. all of the saa7385 control registers, including the 53cf94 control registers appear within this space. 7.2 53cf94 fast scsi controller the details of operation of this block may be found in the 53cf94 data manual . two deviations from the operation of a normal 53cf94 have been made. the first is that the part supports single-ended scsi bus operation only. the second deviation is the additional feature of mapping the control registers into the 80c32 special function register map as previously mentioned. 7.3 input clock doubler to facilitate compatibility of the saa7385 with the maximum number of cd decoders, a clock doubler has been included. this clock doubler may take a 16.9344 mhz clock and double this when requested to do so by the microcontroller. logic has been included to remove the possibility of a runt clock pulse when the doubler is engaged. once engaged, the only way to disengage it is via a reset condition. 7.4 front-end the front-end is comprised of many sub-sections. 7.4.1 b lock decoder the block decoder first reverses the bits of each received byte and then runs them through a linear feedback shift register to be de-scrambled. the polynomial used to de-scramble the serial data is as follows: x 15 +x+1 it also detects and tests the synchronization field and will start the data clock when commanded. the de-scrambled header is assembled into four registers (mode, mins, secs and frms) with header ready and header error status (see hdrrdy and hdrerr in rddstat). the data clock does not have to be enabled to receive valid headers. also included in this section is the logic required to decide when to start collecting data and sub-code information taken from the synchronization signal. 7.4.2 s ector sequencer the sector sequencer de-serializes the data and error flags from the block decoder and determines when to: write data to the buffer write flags to the buffer test the header to determine the mode test the sub-header to determine the form test the crc end the sector and write the status byte to the buffer. included in the sector sequencer is the crc generator which checks each yellow book or green book sector as it is shifted into the saa7385 in accordance with the following polynomial: x 32 +x 31 +x 16 +x 15 +x 4 +x 3 +x+1 the status of each sector is saved and written to the buffer at the end of the sector. 7.4.3 s ub -c ode r eceive a nd q-c hannel e xtractor a uart which samples asynchronous bits on a 24 clocks per bit basis is included. this is required because philips decoders output the sub-code data at nominally 24 clocks per bit, but not synchronized to the data. also included is a sub-code synchronization detector which senses the beginning of each new sector of sub-code information. the serial sub-code information is assembled into bytes in the following order: data bits 7 to 0 = 0, q, r, s, t, u, v and w. as each byte is assembled, it is sent to the buffer manager to be written to the dram buffer. at the same time, the q-channel bits are assembled into bytes and sent to the buffer. all q-channel bytes except crc are sorted in registers for use by the microcontroller. the track, mode, minutes, seconds and frames bytes (rdtk, rdmd, rdmn, rdsc and rdfm) are also stored in registers for use by the microcontroller. the q-channel crc (last two bytes) is checked just before the end of the sub-code sector. if the crc check fails, badq in rddstat is available to the microcontroller and is written into the buffer at the end of the sector. when the five q-channel registers have been updated, qfrmrdy in rddstat is set. the five q-channel registers are valid while qfrmrdy is set. in the audio mode, hdrrdy in rddstat generates this interrupt, but the qfrmrdy bit will still be available as status to the microcontroller.
1996 jun 19 12 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (sequoia) saa7385 7.4.4 c-f lag r eceiver the c-flag bits, or corrector flags, are also 24 data clocks long and reception of these bits is achieved using the same method as for the sub-code; in this event, the c-flag data is synchronized to the data. the difference is that only one bit is used; f1, the absolute time synchronization information. when in audio mode and enabred in fectl is set, receipt of f1 set will start the internal data clock after the next rising edge of word strobe (wsab) which is the left channel sample when the cd decoder is programmed for eiaj audio format. when in audio mode, the q-channel information provides the msf address and the f1 flag provides the start of frame information; together these provide an absolute byte address on the disc. 7.4.5 s2b uart this uart is provided for remote debugging of the firmware. it is hard-wired for one start-bit, eight data bits, a parity bit and one stop bit. parity testing can be programmed to be either odd parity or even parity. parity error and over-run status are provided via pe and ovrrun in s2bstat. selectable baud rates of 31.25, 62.5 and 187.5 kbaud are available via icesel1 and icesel0 in brgsel. 7.4.6 w atch - dog t imer a pair of counters are included which output a 967 m s reset pulse to the entire chip and the sysres pin if the timer is not reset during the 212 ms time-out period. the watch-dog timer is reset by setting rwmd in fectl high then low. if rwmd is left high, the watch-dog function is disabled. 7.4.7 g lue l ogic (glic) the final block of logic in the front-end consists of: a programmable, linear pulse-width modulator for spindle-motor control; an address de-multiplexer for the address/data bus of the microcontroller; plus audio multiplexing and muting circuitry for full control of red book audio data to an external digital-to-analog converter (dac). 7.4.8 b uffer m anager the buffer manager provides the arbitration for the different processes that wish to access the dram buffer. these processes include the front-end, microcontroller requests, ecc accesses, scsi interface requests and dram refreshing. the dram control logic will start an access on the next rising edge of the clock after a request is received. if two or more requests are pending then the priority is as follows: 1. front-end (highest priority) 2. microcontroller requests 3. scsi interface requests 4. ecc requests (lowest priority). a refresh cycle is required every 15.6 m s and will be granted priority for one access. a burst access by ecc or scsi will only be interrupted by a higher priority access request. in addition to the priority logic, logic is required for the front-end sources of data. the priority is: frame data (highest), flag data, sub-code data, q-channel data and finally status byte. all front-end sources are granted priority over the scsi logic, ecc, refresh and data will be written into the frame store during the next cycle. however, the microcontroller has priority over the lower three front-end sources and will be granted an access after front-end frame data or flag data is written to memory. the required timing (see figs 4 to 11) operate with the industry standard 70 ns drams. the interface is designed to operate with one or two drams using: 256 kbit 4 or 1 mbit 4 devices. if a single dram is connected, all access cycles require a page mode cycle to load both the high and the low nibble of data. with a byte-wide memory attached, a single byte cycle takes five clock cycles of 29.5 ns each, totalling 147.5 ns. in nibble mode, a single byte cycle takes 236 ns.
1996 jun 19 13 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (sequoia) saa7385 fig.4 nibble access read cycle. handbook, full pagewidth mge390 doe address row col col data cas ras clock latch low nibble latch high nibble fig.5 nibble access write cycle. handbook, full pagewidth mge391 write address row col col low-nibble high-nibble data cas ras clock
1996 jun 19 14 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (sequoia) saa7385 fig.6 byte mode single access read cycle. handbook, full pagewidth mge392 doe address row col data cas ras clock latch data fig.7 byte mode single access write cycle. handbook, full pagewidth mge393 write address row col data data cas ras clock
1996 jun 19 15 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (sequoia) saa7385 fig.8 ecc burst access read cycle. handbook, full pagewidth mge394 doe address row col1 col2 col3 col4 data cas ras clock latch latch latch fig.9 ecc burst access write cycle. handbook, full pagewidth mge395 write address row col1 col2 col3 col4 data1 data2 data3 data4 data cas ras clock
1996 jun 19 16 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (sequoia) saa7385 fig.10 scsi standard burst access read cycle. handbook, full pagewidth mge396 doe address row col1 col2 col3 col4 data cas ras clock latch data latch data latch data fig.11 scsi standard burst access write cycle. handbook, full pagewidth mge397 write address row col1 col2 col3 col4 data1 data2 data3 data4 data cas ras clock
1996 jun 19 17 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (sequoia) saa7385 8 microcontroller interface 8.1 microcontroller interface status register table 1 num_cor register: 0xf08e register 0xf08e indicates the number of corrections performed during the most recently executed correct_p_syndromes or correct_q_syndromes command. note that num_cor is only valid after completion of the correct_p_syndromes or correct_q_syndromes command, and becomes invalid upon execution of any other command. table 2 ecc_status register: 0xf086 register 0xf086 provides status information on the current or last ecc command. table 3 ecc_status de?nitions 8.2 microcontroller interface command register table 4 eccctl register: 0xf085 the ecc_command definitions are explained in table 5. mnemonic r/w data byte 76543210 num_cor r num_cor7 to num_cor0 mnemonic r/w data byte 76543210 ecc_status r --- flg_eq0 crc_eq0 ps_eq0 qs_eq0 ecc_act mnemonic description ecc_act asserted while a command other than assert_abort or release_abort remains active qs_eq0 asserted when all q syndromes are zero ps_eq0 asserted when all p syndromes are zero crc_eq0 asserted when the crc remainder calculated by the crc_calculate command is all zeros flg_eq0 asserted when all ?ag bytes in ecc ram are zero mnemonic r/w data byte 76543210 eccctl r/w --- - ecc_command3 to ecc_command0
1996 jun 19 18 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (sequoia) saa7385 table 5 de?nitions of ecc_command3 to ecc_command0 table 6 command descriptions eec_command description 0000 assert_abort 0001 release_abort 0010 calculate_syndromes (not mode 2, form 1) 0011 calculate_syndromes (mode 2, form 1) 0100 crc_recalculate (not mode 2, form 1) 0101 crc_recalculate (mode 2, form 1) 0110 copy_results (not mode 2, form 1) 0111 copy_results (mode 2, form 1) 1000 correct_p_syndromes 1001 correct_q_syndromes 1100 test_ecc_rom 1101 test_ecc_ram_read 1110 test_ecc_ram_write command description assert_abort terminates any currently active operation and re-initializes the ecc logic. remains in reset state until occurrence of the release_abort command. at power-on reset, the ecc is in the assert_abort state. all microcontroller status bits are reset when the ecc is in the assert_abort state. release_abort terminates the assert_abort command and enables activation of other commands. crc_recalculate calculate crc remainder buffer data, storing result in ecc ram and updating microcontroller status bit crc_eq0. mode 2, form 1 uses address 16 : 2075, or 0 : 2067; note 1. calculate_syndromes prepares buffer for correction, calculates p and q syndromes, and copies error ?ags and crc remainder from buffer to ecc ram. the microcontroller status bits ps_eq0, qs_eq0 and flags_eq0 are updated at the end of this operation. 1. copy header from buffer to ecc ram (mode 2, form 1 only) 2. write to the buffer. not mode 2, form 1: address 0 ? 0x00; addres s1:10 ? 0xff; address 11 ? 0x00; address 2068 : 2075 ? 0x00 mode 2, form 1: address 0 ? 0x00; ad d1:10 ? 0xff; add 11 : 15 ? 0x00 3. read header and frame data from buffer to calculate p and q syndromes psyn[0 : 85].s1, psyn[0 : 85].s0, qsyn[0 : 51].s1 and qsyn[0 : 51].s0, storing results in ecc ram; see table 76 4. copy error ?ags from buffer to ecc ram 5. copy crc remainder from buffer to ecc ram 6. update microcontroller status bits ps_eq0, qs_eq0 and flags_eq0.
1996 jun 19 19 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (sequoia) saa7385 note 1. 16 : 2075 and 0 : 2067 are address frame offsets. the frame buffer organization is shown in table 75. 8.3 microcontroller interrupts an interrupt pulse is generated upon completion of any of the following commands: calculate_syndromes (not mode 2, form 1) calculate_syndromes (mode 2, form 1) crc_recalculate (not mode 2, form 1) crc_recalculate (mode 2, form 1) copy_results (not mode 2, form 1) copy_results (mode 2, form 1) correct_p_syndromes correct_q_syndromes test_ecc_rom test_ecc_ram_read test_ecc_ram_write. if a command is aborted by the assert_abort command, a spurious interrupt may be generated within five clock cycles of the assert_abort command. copy_results copies current ecc ram contents to the buffer memory: 1. copy header ?ags from ecc ram to buffer (mode 2, form 1 only) 2. copy error flags from ecc ram to buffer 3. copy crc remainder from ecc ram to buffer 4. copy p syndromes from ecc ram to buffer 5. copy q syndromes from ecc ram to buffer. correct_p_syndromes scan all p syndromes and perform p-syndrome calculation. the microcontroller status bits ps_eq0, qs_eq0 and flags_eq0 are updated at the end of this operation. correct_q_syndromes scan all q syndromes and perform q-syndrome calculation. the microcontroller status bits ps_eq0, qs_eq0 and flags_eq0 are updated at the end of this operation. test_ecc_rom read each exponent and log in the alpha rom to the num_cor register. this command may only be terminated by the assert_abort command. test_ecc_ram_read read ecc ram addresses 0 : 591 and copy to buffer addresses 0 : 591. test_ecc_ram_write read buffer addresses 0 : 591 and copy to ecc ram addresses 0 : 591. command description
1996 jun 19 20 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (sequoia) saa7385 table 7 command execution times all times indicated reflect two clock cycles per memory access for all accesses other than p and q corrections. p and q corrections reflect seven clock cycles per memory access. execution times will be extended due to refresh timing, other buffer traffic, and configuration of nibble-wide memory. 8.3.1 i nterrupt register definitions two registers are used to control the operation of the interrupt logic. the register intrmsk allows each interrupt to be enabled or disabled. intrmsk and intrflg are cleared on reset to initially disable and clear all interrupts; the output latch controlling the int line is set on a reset; this must be cleared by writing 0x00 to intrflg. to enable an interrupt, the bit that corresponds to the interrupt in intrflg must be set. the intrflg register shows the status of the interrupts. if any bit is high then an interrupt has occurred since the last time the bit was cleared. writing a zero to any bit location in intrflg will clear the corresponding interrupt. if a masked interrupt occurs, the microcontroller can still detect the occurrence because the event is still posted in intrflg. table 8 interrupt mask register: 0xf0fb each bit in register 0xf0fb corresponds to the interrupt at the same bit location in register 0xf0fc. to enable an interrupt, the bit in this register must be set high. table 9 interrupt ?ag register: 0xf0fc if any bit is set in this register (table 9) then an interrupt may be sent to the microcontroller. table 10 shows when the interrupts are asserted; assuming the corresponding mask bit is set. command cycles time ( m s) at 33 mhz memory accesses calculate_syndromes (not mode 2, form 1) 5604 186.8 2658 calculate_syndromes (mode 2, form 1) 5600 186.7 2654 crc_recalculate (not mode 2, form 1) 4136 137.9 2068 crc_recalculate (mode 2, form 1) 4120 137.3 2060 copy_results (not mode 2, form 1) 1148 38.3 574 copy_results (mode 2, form 1) 1156 38.5 578 correct_p_syndromes (maximum addition per correction) 1466 157 48.9 5.2 0 2 correct_q_syndromes (maximum addition per correction) 888 167 29.6 5.6 0 2 test_ecc_ram_read 1184 39.5 592 test_ecc_ram_write 1184 39.5 592 mnemonic r/w data byte 76543210 intrmsk r/w mask7 mask6 mask5 mask4 mask3 mask2 mask1 mask0 mnemonic r/w data byte 765 4 321 0 intrflg r/w - fetxint ferxint ecc_cor fe_hdr fe2352 str_lst frm_str
1996 jun 19 21 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (sequoia) saa7385 table 10 intrflg ?eld descriptions 8.4 microcontroller ram organization micfrm# is used to determine the frame address for the microcontroller access through the frame window 0x8000 to 0x8fff. to obtain the actual byte location within the buffer ram, the lower 12 bits of the microcontroller address form the relative offset and hence the absolute address is found. note that the microcontroller has the option of addressing memory in a linear fashion using the 32 kbyte address space between 0x000 and 0x7fff. if this 32 kbyte page is used, the pagereg must be programmed with the required page address. pagereg is used to select the required page when the microcontroller makes a linear access to the buffer memory using the address space 0x7000 to 0x7fff. the actual address is the fifteen lsbs from the microcontroller plus 32768 times the value in pagereg. table 11 microcontroller frame number address registers: 0xf0f6 and 0xf0f7 registers 0xf0f6 and 0xf0f7 provide the frame number address for the microcontroller access to memory. the counter associated with these registers is loaded after the most significant byte is written; the least significant byte must be written first to ensure that the counter is loaded correctly. if a dram access is in progress that uses the address from the counter, the update will be delayed until the access is complete. field description frm_str set one when one complete frame is stored str_lst set at the start of the last frame fe_2352 set if the front-end data exceeds 2352 bytes fe_hdr front-end interrupt for header (or q channel) ready ecc_cor ecc interrupt for correction complete rferxint front-end interrupt for receive ready fetxint front-end interrupt for transmit ready mnemonic r/w data byte 76543210 micfrm# r/w num7 num6 num5 num4 num3 num2 num1 num0 micfrm# r/w ------- num8
1996 jun 19 22 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (sequoia) saa7385 table 12 microcontroller address page register: 0xf0ff note 1. page_en is disconnected. register 0xf0ff is used by the buffer manager for the upper address lines when the microcontroller addresses non-frame memory. these registers overlap frame memory, so register 0xf0ff must be programmed with an address in the top part of the memory if no overlap is required. the microcontroller page address line is selected from this register. the outputs are used directly to control dram access cycles, and will affect any current dram cycle in progress. it is possible to access three contiguous frames from the microcontroller by reading the three data sector windows, 0x8000 to 0x8fff, 0x9000 to 0x9fff and 0xa000 to 0xafff. this function is required for the decoding of the sub-code information. if the next frame wraps past the last frame pointer (lastfrm) then the pointers are modified to wrap back to the start pointer onwards (fefrm#); this section is transparent to the microcontroller. table 13 program memory control register: 0xf09f register 0xf09f controls a system test feature where an sram is used for the 80c32 external program memory; note dataprg must be set for any of these features to be enabled. table 14 prgmem ?eld descriptions mnemonic r/w data byte 76 5 43210 pagereg r/w -- page_en (1) ma_19 ma_18 ma_17 ma_16 ma_15 mnemonic r/w data byte 76543210 prgmem r/w dataprg en_win sel_top inv_a15 ---- field logic description inv_a15 0 normal operation 1 invert a(15) to program memory for data memory access sel_top 0 select bottom 32 kbyte window 1 select top 32 kbyte window en_win 0 windowing disabled 1 32 kbyte windows are enabled and sel_top is used to determine window selected dataprg 0 normal operation 1 data memory is mapped to program memory and data memory dram accesses are disabled
1996 jun 19 23 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (sequoia) saa7385 table 15 saa7385 address map details for the 80c32 address function 0000 to 7fff this 32 kbyte window is used to address and portion the dram buffer. it is intended for non-frame mapped memory to be addressed through this window. the upper page address bits (to address the full range of the dram buffer) are set by the linear address page register (pagereg). 8000 to 8fff all accesses to frame memory use this window to read or write to the buffer memory. the actual address to the dram buffer is micro frame number (micfrm#) times 3 k plus the 12 lsbs from the 80c32. 9000 to 9fff this frame window is identical to the frame 0 window with the exception that one is added to the value from the micro frame number (micfrm#). a000-afff this frame window is identical to the frame 0 window with the exception that two is added to the value from the micro frame number (micfrm#). b000-efff not used; outputs are driven low f000-ffff saa7385 control registers fig.12 address map for the microcontroller. handbook, halfpage mge398 0000 7fff 8000 9000 a000 afff ffff f000 80c32 scratch pad ram data sector window (frame 0) data sector window (frame 1) data sector window (frame 2) saa7385 control registers
1996 jun 19 24 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (sequoia) saa7385 9 front panel and miscellaneous control signals this chapter describes the various saa7385 control signals; front panel and basic engine signals, jumper settings and use of the general purpose signals. table 16 start clock doubler: 0xf091 a write of any value to this address will engage the clock doubler. the state of the doubler may be obtained by reading c_34_16 in brgsel (see table 30). if this bit is set then the clock doubler is engaged. on power-on, the clock doubler is disabled. once the clock doubler is engaged, it can only be reset by one of the reset sources; a power-on reset, a scsi reset or a reset from the watch-dog timer. the clock doubler must not be engaged when a 33.8688 mhz clock is connected to oscin (pin 117). table 17 frequency synthesizer test register: 0xf0d8; note 1 note 1. register 0xf0d8 is used for ic-level testing and to power down the frequency synthesizer. only bit use_in should be asserted in normal operation. table 18 fstest ?eld description table 19 disconnected pulse-width modulator control: 0xf0b3; note 1 note 1. register 0xf0b3 is disconnected. mnemonic r/w data byte 76543210 clksel w -------- mnemonic r/w data byte 76543210 fstest r/w -- use_in cpsel fvcod fs_lock -- field logic description fs_lock 0 normal operation 1 3-state led and switch lqdata to fs_lock fvcod 0 normal operation 1 test mode for fvcod from the synthesizer cpsel 0 normal operation 1 test mode for cpsel from the synthesizer use_in 0 use internal synthesizer 1 power down the synthesizer and operate off a 33.87 mhz input clock mnemonic r/w data byte 76543210 wtpwm r/w --------
1996 jun 19 25 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (sequoia) saa7385 table 20 general logic control register: 0xf0b9; note 1 note 1. register 0xf0b9 controls the audio mixing and the led. table 21 wtgctl ?eld description table 22 drive switches register: 0xf0ba; note 1 note 1. register 0xf0ba is used for sensing the drive switches. table 23 rdsw ?eld description table 24 jumper status register: 0xf0c9; note 1 note 1. the bit fields for the jumpers are explained in table 25. mnemonic r/w data byte 76 5 4 3 2 1 0 wtgctl w -- pwmsel led la_mute ra_mute channel1 channel0 field logic description channels 00 mute 01 right data sent to both channels 10 left data sent to both channels 11 stereo ra_mute - right channel digital mute la_mute - left channel digital mute led - active low control for the light emitting diode pwmsel - pwm is disconnected mnemonic r/w data byte 76543210 rdsw r --- pla y skipfwd skipback eject tra ysw field logic description tra ysw 0 tray position in 1 tray position out eject - user is requesting the drive tray to open (active low) skipback - user is requesting a track skip backwards (active low) skipfwd - user is requesting a track skip forwards (active low) pla y - user is requesting the drive to play (active low) mnemonic r/w data byte 76543210 rdjmprs r jumper7 to jumper0
1996 jun 19 26 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (sequoia) saa7385 table 25 rdjmprs ?eld description table 26 general purpose bits: 0xf0c2; note 1 note 1. register 0xf0c2 controls the direction and output state of the general purpose i/o bits on the saa7385. reading the gpio direction bits reflects the last value that was written to the register. the four gpio data bits shows the current value of the input signals in the input mode. in the output mode, the last value written to the output latches is that which is read back. table 27 gpioctl ?eld description field description jumper7 to jumper0 indicates the value of the dram data bus on power-up. the data bus may be pulled high or low using weak pull-ups and pull-downs hence up to eight jumper settings are accommodated. mnemonic r/w data byte 76543210 gpioctl r/w gpdat4 gpdir4 gpdat3 gpdir3 gpdat2 gpdir2 gpdat1 gpdir1 field description gpdir1 general purpose bit direction control. default low puts gpio1 into the input mode, setting this high puts gpio1 in output mode. gpdat1 gpio1 data bit. gpdir2 general purpose bit direction control. default low puts gpio2 into the input mode, setting this high puts gpio2 in output mode. gpdat2 gpio2 data bit. gpdir3 general purpose bit direction control. default low puts gpio3 into the input mode, setting this high puts gpio3 in output mode. gpdat3 gpio3 data bit. gpdir4 general purpose bit direction control. default low puts gpio4 into the input mode, setting this high puts gpio4 in output mode. gpdat4 gpio4 data bit.
1996 jun 19 27 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (sequoia) saa7385 9.1 s2b uart registers this section describes the registers used for the s2b uart control. table 28 s2b uart transmit, receive and status buffer: 0xf0a1, f0a2 and f0a3 note 1. wts2b is for the transmit data byte from the s2b uart and rds2b is for the receive data byte from the s2b uart. table 29 s2bstat ?eld description table 30 baud rate generator control: 0xf0c0; note 1 note 1. register 0xf0c0 controls the s2b uart baud rate and selective inversion of the sub-code information. control over the parity and the clock doubler is also included together with the ability to invert the sub-code and q-channel information. mnemonic r/w data byte 76543210 wts2b (1) w data7 data6 data5 data4 data3 data2 data1 data0 rds2b r data7 data6 data5 data4 data3 data2 data1 data0 s2bstat r -- spr cpr txdrdy pe ovrrun rxdrdy field description rxdrdy a logic 1 indicates that the receive data is valid. ovrrun a logic 1 indicates that the data in the receive buffer was not read before it was over written by the next byte. pe a logic 1 indicates that a parity error was detected in the receive data byte; this is usually caused by the wrong baud rate. txdrdy a logic 1 indicates that the transmit data buffer is empty and ready for another byte. cpr s2b handshake bit which may be interpreted as clear to send; this is generated automatically by the uart. it is asserted whenever the uart receiver is ready for a byte and negated as soon as the stop bit is shifted in. it is again asserted as soon as the received byte is read by the 80c32. spr s2b handshake bit which may be interpreted as request to send; this is received from the cd-rom engine uart transmitter and will generate an interrupt to the 80c32 if the txrdy bit is set and the interrupt is not masked. mnemonic r/w data byte 76543210 brgsel r/w c_34_16 lock evenpar invsubc invq - icesel1 icesel0
1996 jun 19 28 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (sequoia) saa7385 table 31 brgsel ?eld description table 32 uart special control register: 0xf09e; note 1 note 1. register 0xf09e allows the 80c32 uart clock to be derived from 16.945 mhz. this external uart clock is required for reliable operation of the uart if the 80c32 is used for other functions during the transfer. table 33 uartctl ?eld description field logic description icesel1 to 0 00 31.25 kbaud transfer rate 01 62.5 kbaud transfer rate 10 187.5 kbaud transfer rate 11 not speci?ed invq - inverts all q-channel information if set invsubc - inverts all sub-code information if set evenpar - selects even parity for s2b uart is set lock - read only information; indicates clock synthesizer is stable (after reset) and it is ready to set c_34_16 c_34_16 - once lock is high, asserting this bit engages the clock doubler mnemonic r/w data byte 7 6 543210 uartctl r/w extuart uartcnt divide5 divide4 divide3 divide2 divide1 divide0 field logic description divide5 to 0 - value 0 produces a 0.264 mhz clock and 58 produces a 2.82 mhz clock for the uart; this is the maximum accepted by the 80c32, a smaller number is required for guaranteed operation e.g. 15 uartcnt 0 normal uart data input sampled by the external clock 1 select a uart data input sampled by the clock from the internal counter extuart 0 use external uart clock; disables internal clock 1 switch external uart clock input from pin to this internal counter
1996 jun 19 29 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (sequoia) saa7385 9.2 miscellaneous control registers table 34 53cf90 direction and audio mode control: 0xf0c1; note 1 note 1. register 0xf0c1 controls the audio mode byte swapping and a test mode bit. table 35 wtdir ?eld descriptions table 36 scsi mode control register: 0xf0fd; note 1 note 1. register 0xf0fd controls the operation of the interface to the scsi controller. the outputs of these registers are used to directly control dram access cycles, and will affect any current dram cycle in progress. table 37 scsimod ?eld description mnemonic r/w data byte 7 6 543210 auswp r/w test --- over4x bsb -- field description bsb byte swap bit. defaults to swapping the most signi?cant byte and least signi?cant byte in the audio mode such that the least signi?cant byte of all audio samples is stored at even addresses in the dram. setting this high causes the audio data to be stored in the same way as in the data mode. over4x 4 over-sampling bit selection; default low select transmit, or no over-sampling, mode for the sub-code and c-?ag uarts. setting this bit high will cause the sub-code and c-?ag data to be sampled at one quarter the data rate allowing q-channel information to be correctly stored in the registers while the cd-60 is outputting audio data at 4 over-sampling. test enables internal signals to be multiplexed out when the test pin (pin 125) is high. mnemonic r/w data byte 76543210 scsimod r/w --- off_adr off_end off_str rd_buf byt/pag field logic description byt/pag 0 scsi dram byte mode access 1 scsi dram page mode access rd_buf 0 scsi read/write control; read from buffer memory 1 scsi read/write control; write to buffer memory off_str 0 scsi offset start a/b control; select a registers 1 scsi offset start a/b control; select b registers off_end 0 scsi offset end a/b control; select a registers 1 scsi offset end a/b control; select b registers off_adr 0 scsi transfers use only a registers 1 scsi transfers use a and b registers
1996 jun 19 30 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (sequoia) saa7385 table 38 dram selection/test mode: 0xf0fe; note 1 note 1. after power-up or reset, dramsel should be the first register that is programmed. this register is used to select the number and the type of drams used. the output of this register is used to control the dram access directly and will affect any current dram cycle. table 39 scsimod ?eld description mnemonic r/w data byte 76543 2 1 0 dramsel r/w test restest3 to restest0 dbl_spd 1_meg 2_drams field logic description 2_drams 0 single dram used 1 two drams used 1_meg 0 256 k 4 11m 4 dbl_spd 0 single speed refresh; condition after reset 1 double speed refresh; only set if system is running at 0.5 master clock speed restest3 to restest0 - reserved for test: enable dram access test; switch multiplexer control, enable interrupts test 0 normal operation 1 test mode; read back of restest3 to restest0 is gated by this bit
1996 jun 19 31 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (sequoia) saa7385 10 front-end this chapter explains the information of the front-end circuitry. 10.1 minute second frame (msf) addressing and header information table 40 header mode and msf from block decoder: 0xf092, f093, f09a and f09b these registers contain the mode, minute, second and frame information from the header when in data mode. this data is valid whenever the hddrdy bit in the rddstat register is set. in audio mode, the msf address is taken from the q-channel information. table 41 q-channel information: 0xf0a9, f0aa, f0ab, f0b1 and f0b2 these registers contain the information taken from the raw sub-channel information from the cd decoder. due to the fact that this data has not had any error correction applied to it, it is necessary to perform a crc check for validity. twelve bytes of q-channel information are assembled from each sector of data; the last two bytes contain the crc parity. therefore the validity of the contents of these registers can only be determined after the last bit has been loaded and checked. mnemonic r/w data byte 76543210 mode r mode7 to mode0 mins r minutes7 to minutes0 secs r seconds7 to seconds0 frms r frame7 to frame0 mnemonic r/w data byte 76543210 rdtk r track7 to track0 rdmd r mode7 to mode0 rdmn r absmin7 to absmin0 rdsc r abssec7 to abssec0 rdfm r absfrm7 to absfrm0 table 42 times from qchrdy to badq (rddstat) speed time ( m s) n = 1 2177 n = 2 1089 n = 4 545 n = 6 363 n = 8 273 for example, at the n = 4 data rate, the badq flag (in rddstat) should be checked 545 m s after the qfrmrdy interrupt (from rddstat) is asserted. if badq is low then the contents of the q-channel registers are valid; otherwise the crc check failed and the q-channel information may be incorrect. if the data clock is running (ecmd low or enabred high) then badq will be valid until the end of the sector; otherwise badq is valid until the end of the next q frame.
1996 jun 19 32 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (sequoia) saa7385 10.2 front-end status and control table 43 front-end control: 0xf0bb; note 1 note 1. register 0xf0bb controls the front-end of the saa7385. the naming convention used here is similar to that used in the block decoders. table 44 fectl ?eld description mnemonic r/w data byte 7654 3 2 1 0 fectl r/w sim_eof rsmd break rwmd enabred audmode synasyn ecmd field logic description ecmd 0 data is shifted in and stored when the next synchronization pattern is detected; ( synasyn = 1 and audmode = 0). 1 data ?ow stop just before next synchronization pattern. ecmd is set on a reset condition; ( synasyn = 1). synasyn synchronous/asynchronous selection; this controls the method by which data is started and stopped by the block decoder, only operates in data mode. 0 causes a panic stop. a partial frame will reside in current and subsequent buffers unless sim_eof is set then cleared; (ecmd = 1). 1 data is started and stopped on frame boundaries (on synchronization patterns). audmode 0 data mode. cleared on reset. 1 audio mode, where the bit clock is shifted to accommodate eiaj format. hqrdy in intrflg follows hdrrdy in data mode and qfrmdry in audio mode. enabred enable red book to data path; while in audio mode, this is equivalent to ecmd in the data mode. no asynchronous stop is provided in the audio mode. 0 data ?ow will stop when the next f1 c-?ag is detected. cleared on a reset condition. 1 red book data is input to buffer after the detection of the next f1 c-?ag. rwmd - this must be pulsed high then low every 212 ms to prevent the watch-dog timer from resetting the saa7385 and the drive. the length of the reset pulse is 967 m s. if rwmd is set, the watch-dog timer is disabled. break - when set, the s2b uart transmitter output is held high. rsmd - when the pulse is high then low, the block decoder begins to search for a synchronization pattern in the data bitstream. once a synchronization pattern is found, mode, mins, secs, and frms become valid. sim_eof - this provides a ?rmware reset to the frame sequencer and parts of the buffer manager. this would be required if an asynchronous stop of the data stream occurs. pulsing this high then low resets all counters and establishes a beginning of frame state. dcoact in rddstat must be low to allow sim_eof to have any effect. if sim_eof is set, no data or sub-code is stored in the buffer.
1996 jun 19 33 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (sequoia) saa7385 table 45 read status register: 0xf0c3; note 1 note 1. the information in register 0xf0c3 is a copy of the status byte written to the data buffer at the end of every frame. syncerr, daterr and crcerr are essentially unusable since they are valid only long enough to be written to the buffer. table 46 rddstat ?eld description mnemonic r/w data byte 7 6 5 432 1 0 rddstat r dcotact badq qfrmrdy hdrrdy hdrerr crcerr daterr syncerr field logic description syncerr 0 good synchronization detected (valid for 120 ns at the end of a sector). daterr 0 good data (valid for 120 ns at the end of a sector). crcerr 0 good crc (valid for 120 ns at the end of a sector). hdrerr 0 good header. if the automatic storage is selected, assertion of hdrerr inhibits data storage. 1 efab during reception of header (valid while hdrrdy set). if the automatic storage is selected, assertion of hdrerr inhibits data storage. hdrrdy - when set, a valid header is available. if the header is not read within a frame time, this remains set until the next synchronization pattern and will be set again when the next header arrives. it is cleared when any of the header bytes are read. this bit generates an interrupt to the microcontroller when in data mode. qfrmrdy - when set, all ten q-channel bytes are received waiting to be read (badq is known). it is reset at the end of frame or when any of the q-channel bytes are read. this bit generates an interrupt to the microcontroller when in audio mode. badq - if q-channel information failed crc then badq is set. it is reset on next good crc check or on end of frame if dcoact is running. if dcoact is not running (i.e. audio mode) badq is reset on next detection of sub-code gap. if autostr in wtdir is selected, assertion of badq inhibits audio data storage. dcotact - set when data is being shifted an and stored in the buffer: this will remain high for the entire transmission.
1996 jun 19 34 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (sequoia) saa7385 11 buffer manager 11.1 front-end to buffer manager interface the buffer manager interface to the front-end is write only with no handshaking. the front-end passes one byte of data and a write strobe to the buffer manager; this byte will be one of five types of data (see table 47). the data byte is latched and the interface is given the highest priority thus no wait signal is required. the other signals passed from the front-end logic are an end-of-frame strobe (which is the same as the status byte write strobe), a software-generated reset pulse (used to reset the front-end counters), and a reset pulse for the q-channel and sub-code offset counters. the buffer manager provides the remainder of the logic to write the data into the ram and keep track of the frame addresses and offset addresses. this logic consists of a 12-bit frame offset counter feoff, for data and an 9-bit frame counter; this is a relative frame number and is not related to the cd-rom frame number. offset counters are also provided for the four other types of data. the other offset address generators are based on fixed addresses, and they will be loaded with the start address at the beginning of each frame. the five types of data from the front-end are loaded into the frame map as shown in table 47. table 47 data types from the front-end initially the front-end frame counter and all of the offset counters are cleared by reset or loaded with the contents of fefrm# when the last frame as specified by lastfrm is filled; therefore fefrm# should be loaded with the required starting frame number. the data frame offset counter, fefrmoff, may be loaded for test purposes, but is cleared at the end of each frame. lastfrm establishes the limit of the frame memory. this register should be loaded with the required number of frames; the amount of memory used is 3 kbytes times the number of frames. the front-end frame address counter uses this value to determine the correct location to clear the counter. once the data load process starts, the offset counter (fefrmoff) increments after each byte is written into memory. this process continues until an end of frame signal is received from the front-end logic. if an error occurs and the offset counter increments past the maximum 2352, an interrupt will be issued to the microcontroller. table 48 front-end frame offset: 0xf0e2, f0e3 this register allows the front-end frame offset counter to be read and reloaded. the counter associated with these registers is loaded after the most significant byte is written; the least significant byte must be written first to ensure that the counter is loaded correctly. if a dram access is in progress that uses the address from the counter, the update will be delayed until the access is complete. this counter is cleared on reset or after each frame is loaded into buffer memory. therefore, this register should not be loaded during normal operation. start end length data type 0x000 0x92f 0x930 header, data and parity 0x930 0x93f 0x010 q-channel 0x940 0x99f 0x060 sub-channel 0x9a0 0xac5 0x126 error ?ags 0xbde 0xbde 0x001 status byte mnemonic r/w data byte 76543210 fefrmoff r/w offset7 to offset0 fefrmoff r/w ---- offset11 to offset8
1996 jun 19 35 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (sequoia) saa7385 table 49 front-end frame number: 0xf0e4, f0e5 this register allows the front-end frame number counter to be read and reloaded. the counter associated with these registers is loaded after the most significant byte is written; the least significant byte must be written first to ensure that the counter is loaded correctly. if a dram access is in progress that uses the address from the counter, the update will be delayed until the access is completed. this counter is cleared on reset or when the last frame, as specified by lastfrm, is filled. therefore, this register should only be loaded if a non-zero start frame number is required. the frame counter is automatically cleared at the end of the frame buffer memory and thus multiple passes of a non-zero start address will require a re-load for each pass; it is not practical to do this in real-time. table 50 last frame number for storage: 0xf0f8, f0f9 these registers are used by the buffer manager to set the top of frame storage memory (wrap point). any memory past this point is available for general usage by the microcontroller. the outputs of the registers are used directly to control dram access cycles, and will affect any current dram cycle in progress. both the scsi address counter and the front-end frame address counter use this value to determine the correct location to clear their respective frame counters. 11.2 microcontroller to buffer manager interface the microcontroller interface allows the microcontroller to read or write any register or the frame store memory. frame and offset registers are used to update the counters after the most significant byte has been loaded. frame store memory is addressed using a frame number register controller by the microcontroller. logic is provided to allow the frame number of the last complete frame received (lstcmpfm) from the front-end to be read by the microcontroller for the purpose of setting the microcontroller frame address. memory beyond the last frame number is available to the microcontroller using the microcontroller bottom 32 kbyte located at 0x0000 to 0x7fff. the 4 kbyte segment at 0x8000 to 0x8fff is used to address the current frame memory. also, the next frame may be accessed at 0x9000 to 0x9fff, and the current frame plus 2 may be accessed at 0xa000 to 0xafff. a page register is provided to allow the microcontroller to address the complete memory range in 32 kbyte pages. all microcontroller accesses to memory are single byte read or write cycles. all microcontroller accesses to memory will generate a wait state. if no other accesses to memory are in progress then a minimum wait state cycle will be generated. if, however, other cycles are in progress then the microcontroller is forced to wait until the lower priority access cycles finish and any high priority access cycles are completed. the worst case wait is four complete access cycles; a total of 20 clock cycles in byte mode and 32 cycles in nibble mode. mnemonic r/w data byte 76543210 fefrm# r/w num7 num6 num5 num4 num3 num2 num1 num0 fefrm# r/w ------- num8 mnemonic r/w data byte 76543210 lastfrm r/w num7 num6 num5 num4 num3 num2 num1 num0 lastfrm r/w ------- num8
1996 jun 19 36 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (sequoia) saa7385 table 51 last complete frame number: 0xf0e6, f0e7 11.3 ecc to buffer manager interface the ecc logic is able to access the buffer manager frame memory in either byte or burst mode. the ecc logic provides an offset address and uses a frame address programmed by the microcontroller, eccfrm#. the logic can write a single byte or variable number of bytes. in the event of an access to a variable number of bytes, the ecc logic will assert the signal burst and ereq to indicate that a large number of cycles are requested. for each read or write cycle, the buffer manager will toggle eack high for one clock cycle to indicate that one byte of data has been read from or written to the memory. a single byte cycle will be the same with the exception that burst will remain negated (low). in the event of a higher priority memory access request during a burst cycle, eack will remain low for the duration of the higher priority access cycle. at the end of the higher priority access, the burst cycle will resume and eack will again toggle high after each read or write is completed. table 52 ecc frame number address registers: 0xf0f4, f0f5; notes 1 and 2 notes 1. these registers provide the frame number address for ecc access to memory. the counter associated with these registers is loaded after the most significant byte is written; the least significant byte must be written first to ensure that the counter is loaded correctly. if a dram access is in progress that uses the address from the counter, the update will be delayed until the access is completed. 2. eccfrm# is used to determine the frame address for all ecc operations. this register must be reloaded for each frame accessed by the ecc. mnemonic r/w data byte 76543210 lstcmpfm r num7 num6 num5 num4 num3 num2 num1 num0 lstcmpfm r ------- num8 mnemonic r/w data byte 76543210 eccfrm# r/w num7 num6 num5 num4 num3 num2 num1 num0 eccfrm# r/w ------- num8 11.4 scsi to buffer manager interface the scsi registers should be loaded prior to starting an scsi transfer. the scsimod register should be loaded first. byt/pag from this register is used to control the type of dram access used by the scsi interface. if byt/pag is high then burst mode access cycles are selected; multiple cas access cycles are used to access data as fast as possible. rd_buf from scsimod controls the direction of data flow to the buffer memory; this bit is kept low to allow reading of data from the dram buffer. if rd_buf is asserted then scsi data will be written to the dram buffer. off_adr from scsimod is used to select between one and two offset mode for the scsi transfer. off_adr low selects single offset mode in which one block of data is transferred for each frame of the buffer. the transfer block is specified by registers scsioffs and scsioffe. for each frame, the transfer will start at the address specified by scsioffs and continue until the address specified by scsioffe is transferred. after each block is transferred, the frame address scsicfrm will be incremented and the transfer will continue with the same address block from the next frame. if off_adr is set, then two blocks of data are transferred. in the two offset mode, both scsioffs and scsioffe are used to access two independent register pairs; for simplicity, these are called the a registers and the b registers. in this event, the transfer for each frame is a two step process. first, the offset block specified by scsioffs-a and scsioffe-a is transferred; the transfer address range is from scsioffs-a to scsioffe-a and includes both the start and end addresses. after the first offset block is
1996 jun 19 37 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (sequoia) saa7385 transferred, the second offset block as specified by scsioffs-b and scsioffe-b is transferred. the frame address will not be incremented until after both offset blocks are transferred. once both offset blocks are transferred, the frame address is incremented and again the two offset blocks are transferred for the next frame. reading and writing of the a and the b registers is controlled by an automatic switching after the most significant bytes of the registers are written. after power-up or reset the pointer to the a registers will be selected. if the dual offset mode is selected, the a/b switch will be toggled when the most significant bytes of the registers are written; either the most significant bytes of scsioffs or scsioffe. any future reads or writes will access the b registers. the process of loading and reading the two scsi offset address pairs can be monitored and controlled by off_str and off_end from scsimod. reading off_str shows the status of the a/b switch for the scsioffs-a/b registers; reading off_end shows the status of the a/b switch for the scsioffe-a/b registers. a write to scsimod with off_str low will clear the a/b switch for the scsioffs registers; a write to scsimod with off_end low will clear the a/b switch for the scsioffe registers. scsisfrm is used to determine the starting frame address for all scsi operations. the associated counter is automatically incremented after each frame, and is cleared when the last frame as specified by lastfrm is transferred. to update the scsi frame address counter, scsisfrm must be rewritten. the current scsi frame address is available by reading scsicfrm. the frame counter is automatically cleared at the end of the frame buffer memory and thus multiple passes of a non-zero start address will require a re-load for each pass; it is not practical to do this in real-time. the scsioffs registers access either one or two register pairs as controlled by scsimod. scsioffs determines the starting offset address for a scsi transfer. the scsioffe register accesses either one or two register pairs as controlled by scsimod. scsioffe determines the ending offset address for a scsi transfer. remarks : if two offset pairs are used, the a start offset must be written last to ensure that the correct offset start address is loaded into the counter. in the two offset mode, reading the register after loading is not possible due to the automatic switching feature; if the a offset pair is written, and the register pair is read, the b offset pair would be read. table 53 scsi offset start register (a and b): 0xf0e8, f0e9; note 1 note 1. these registers, together with the offset end registers, allow full control over the number of frame bytes that will be transferred to the scsi port. mnemonic r/w data byte 76543210 scsioffs r/w offset7 to offset0 scsioffs r/w ---- offset11 to offset8
1996 jun 19 38 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (sequoia) saa7385 table 54 scsi offset end registers (a and b): 0xf0ea, f0eb; note 1 note 1. these registers together with the offset start registers, allow full control over the number of frame bytes that will be transferred to the scsi port. table 55 scsi transfer start frame number: 0xf0ec, f0ed; note 1 note 1. this register determines the starting frame number for an scsi transfer. the outputs of the registers are used to directly control dram access cycles, and will affect any current dram cycle in progress. the scsi frame pointer will wrap back to this point. table 56 scsi current transfer frame: 0xf0ee, f0ef; note 1 note 1. this register allows the current scsi frame transfer number to be read. 11.5 miscellaneous buffer manager considerations the following bandwidth limitation must be observed in normal operation: all burst mode operations (scsi and ecc) take twice as long in nibble mode, and single cycle operations take 60% longer; 236 ns compared with 147.5 ns. for this reason, operation of the dram interface at the maximum 8 times transfer rate in nibble mode is not supported. in byte mode, only 833 ns is available between each data write from the front-end at the maximum 8 times transfer rate. at the end of the frame, multiple front-end byte writes may stack up and therefore it is recommended that the 80c32 avoids dram access at the end of the frame. if two scsi offset pairs are used, the a start must be written last to ensure that the correct offset start address is loaded into the counter. in the two scsi offset mode, reading the register after loading is not possible due to the automatic switching feature. mnemonic r/w data byte 76543210 scsioffe r/w offset7 to offset0 scsioffe r/w ---- offset11 to offset8 mnemonic r/w data byte 76543210 scsisfrm r/w num7 num6 num5 num4 num3 num2 num1 num0 scsisfrm r/w ------- num8 mnemonic r/w data byte 76543210 scsicfrm r num7 num6 num5 num4 num3 num2 num1 num0 scsicfrm r ------- num8
1996 jun 19 39 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (sequoia) saa7385 11.6 53cf94 related registers in the 53cf94 scsi controller, some registers are read only and others are write only. these share the same address and the multiplexing between the two depends on the read or write select. this part contains only a brief description of the register definitions. for a more detailed definition, see the data sheet for the scsi device. table 57 transfer count registers: 0xf0a4, f0a5 and f0be- 53cf94 addresses: 0x00, 01, 0e; note 1 note 1. these registers form the 24-bit transfer count value for dma operations; they specify the number of bytes that are transferred. table 58 fifo buffer register: 0xf0a6 - 53cf94 address 0x02; note 1 note 1. the fifo is a 16 9-bit buffer between the scsi interface and the memory. the scsi command packet will be present in this fifo ready to be read by the microcontroller at the end of the scsi command phase. table 59 command register: 0xf0a7 - 53cf94 address 0x03; note 1 note 1. the command register is a two-deep read/write register used to pass commands to the scsi controller; up to two commands can be stacked at the same time. when endma is set, the command is a dma instruction. table 60 status register and destination id: 0xf0ac - 53cf94 address 0x04; note 1 note 1. this register contains the flags indicating the occurrence of certain events. mnemonic r/w data byte 76543210 tclow r/w data7 data6 data5 data4 data3 data2 data1 data0 tcmid r/w data7 data6 data5 data4 data3 data2 data1 data0 tchigh r/w data7 data6 data5 data4 data3 data2 data1 data0 mnemonic r/w data byte 76543210 fifo r/w data7 data6 data5 data4 data3 data2 data1 data0 mnemonic r/w data byte 76543210 cmd r/w endma command6 to command0 mnemonic r/w data byte 76543210 stat r int ge pe tc vgc msg c/d i/o stat w ----- id2 id1 id0
1996 jun 19 40 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (sequoia) saa7385 table 61 stat ?eld description table 62 interrupt register and time-out register: 0xf0ad - 53cf94 address 0x05; note 1 note 1. this register is used in conjunction with stat and seqstp to determine the cause of an interrupt. table 63 int ?eld description table 64 sequence step register and synchronous transfer register: 0xf0ae - 53cf94 address 0x06; note 1 note 1. the register fields are described in table 65. field description msg, c/d, i/o these indicate the phase on the scsi bus. vgc valid group code; set if the group code matches code de?ned in ansi x3.131-1986. tc terminate count; set when transfer count decrements to zero. pe parity error; set if parity checking is enabled and a scsi parity error occurs. ge gross error; set on various error conditions. these errors do not cause interrupts. int interrupt. indicates whether device is trying to interrupt the microcontroller. id2 to id0 speci?es the encode destination for selection or re-selection. mnemonic r/w data byte 76543210 int r srst ilcmd dis bs fc resel satn sel int w timeout7 to timeout0 field description sel selected; set during selection phase if selected as a target with atn negated. satn selected with atn; set during selection if selected as a target with atn asserted. resel reselected; set during reselection phase if reselected as an initiator. fc function complete; set after any target mode command has been completed. bs bus service. indicates that another device is requesting service; in target mode it is asserted whenever the initiator asserts atn. dis disconnect. in target mode this is asserted and as a terminate sequence or a command complete sequence command causes disconnection. ilcmd illegal command; set when a reserved code is placed in cmd or when the command is from a mode group. srst scsi reset detect. this may be set if a reset on the scsi bus is detected. timeout7 to timeout0 time-out period for response to selection or re-selection. mnemonic r/w data byte 76543210 seqstp r ---- som ss2 ss1 ss0 seqstp w --- transperiod4 to transperiod0
1996 jun 19 41 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (sequoia) saa7385 table 65 seqstp ?eld descriptions table 66 fifo ?ags and synchronous offset register: 0xf0af - 53cf94 address 0x07; note 1 note 1. the field description for the fifo flags register is shown in table 67. table 67 fifoflg ?eld descriptions table 68 con?guration registers: 0xf0b4, f0b7, f0bc and f0bd - 53cd94 addresses 0x08, 0b, 0c and 0d; note 1 note 1. the registers described allows the controller to be configured for the specific mode of operation. field description ss2 to ss0 sequence step. counter increments at various points in a command; may be used for error recovery. som synchronous offset maximum. when clear, the synchronous offset has reached the maximum value. transperiod synchronous transfer period. speci?es minimum time between successive req or ack pulses. mnemonic r/w data byte 76543210 fifoflg r ss2 ss1 ss0 ff4 ff3 ff2 ff1 ff0 fifoflg w syncoffset7 to syncoffset0 field description ff number of bytes in the fifo ss duplicates of sequence step register syncoffset controls handshaking in synchronous transfer mode mnemonic r/w data byte 76543210 config1 r/w slow srd ptest pchk ctest mybusid2 to mybusid0 config2 r/w rfb fe ebc dhz scsi2 bpa rpe dpe config3 r/w imrc qte cdb10 fscsi fclk srb adma t8 config4 r/w ----- ean test bbte
1996 jun 19 42 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (sequoia) saa7385 table 69 config1 to config4 ?eld descriptions table 70 clock conversion factor: 0xf0b5 - 54cf94 address 0x09; note 1 note 1. this register must be set in accordance with the clock input frequency. table 71 clock field descriptions field description mybusid id of scsi controller ctest chip test mode enable pchk enable parity checking ptest parity test mode srd scsi reset reporting interrupt disable slow slow cable mode dpe dma parity enable rpe register parity enable bpa target bad parity abort scsi2 allows support for scsi-2 features dhz dreq high impedance ebc enable byte control fe features enable rfb reserve fifo byte t8 threshold eight adma alternate dma mode srb save residual byte fclk fast clock fscsi fast scsi cdb10 allows 10-byte group-2 commands to be recognized qte queue tag enable imrc id message reserve check bbte back-to-back transfer enable test transfer count test mode ean enable active negation mnemonic r/w data byte 76543210 clock w ----- convert7 to convert0 field description convert7 to convert0 clock conversion factor
1996 jun 19 43 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (sequoia) saa7385 table 72 test register: 0xf06 - 53cf94 address 0x0a; note 1 note 1. this register is enabled by setting the test mode in config1; after test mode is entered, a hardware reset or reset command must occur before normal operation may resume. table 73 test ?eld descriptions table 74 fifo bottom: 0xfbf - 53cf94 address 0x0f; note 1 note 1. this register is used during initiator synchronous data in to align 16-bit dma transfers to word boundaries. mnemonic r/w data byte 76543210 test r/w ----- hi-z init tar field description tar target mode init initiator mode hi-z all outputs set to high impedance mnemonic r/w data byte 76543210 fifobtm w data7 data6 data5 data4 data3 data2 data1 data0
1996 jun 19 44 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (sequoia) saa7385 12 frame buffer organization table 75 frame buffer organization table 76 ecc ram organization decimal hexadecimal data start end len start end len 0 11 12 000 00b 00c synchronization ?eld 12 15 4 00c 00f 004 header 16 2063 2048 010 80f 800 frame data 2064 2067 4 810 813 004 crc parity 2068 2075 8 814 81b 008 padding 2076 2247 172 81c 8c7 0ac p parity 2248 2351 104 8c8 92f 068 q parity 2352 2367 16 930 93f 010 q channel 2368 2463 96 940 99f 060 sub-channel 2464 2757 294 9a0 ac5 126 error ?ags 2758 2761 4 ac6 ac9 004 crc remainder 2762 2933 172 aca b75 0ac p syndromes 2934 3037 104 b76 bdd 068 q syndromes 3038 3038 1 bde bde 001 status dec hex byte number 3210 000 000 psyn[00].s1 psyn[00].s0 qsyn[00].s1 qsyn[00].s0 204 0cc psyn[51].s1 psyn[51].s0 qsyn[51].s1 qsyn[51].s0 208 0d0 psyn[52].s1 psyn[52].s0 ?ags[001] ?ags[000] 340 154 psyn[85].s1 psyn[85].s0 ?ags[067] ?ags[066] 344 158 ?ags[071] ?age[070] ?ags[069] ?ags[068] 564 234 ?ags[291] ?age[290] ?ags[289] ?ags[288] 568 238 unused[1] unused[0] ?ags[293] ?ags[292] 572 23c crc_rem[3] crc_rem[2] crc_rem[1] crc_rem[0] 576 240 header[3] header[2] header[1] header[0] 580 244 ecc_reg[03] ecc_reg[02] ecc_reg[01] ecc_reg[00] 584 248 ecc_reg[07] ecc_reg[06] ecc_reg[05] ecc_reg[04] 588 588 ecc_reg[11] ecc_reg[10] ecc_reg[09] ecc_reg[08]
1996 jun 19 45 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (sequoia) saa7385 13 summary of control register map table 77 control register map for the saa7385 address mnemonic read/write description f085 eccctl r/w ecc control register f086 eccstat r ecc status register f08e num_cor r ecc register for the number of corrections f091 clksel w start the clock synthesizer (doubler) f092 mode r header mode byte from block decoder f093 frms r header frame byte from block decoder f09a secs r header seconds byte from block decoder f09b mins r header minutes byte from block decoder f09e uartctl r/w uart special control registers f09f prgmem r/w program memory control registers f0a1 wts2b w s2b uart transmit buffer f0a2 rds2b r s2b uart receive buffer f0a3 s2bstat r s2b uart status register f0a4 tclow r/w 53cf94 (00); transfer counter low f0a5 tcmid r/w 53cf94 (01); transfer counter middle f0a6 fifo r/w 53cf94 (02); fifo f0a7 cmd r/w 53cf94 (03); command register f0a9 rdtk r q channel track number f0aa rdmd r q channel mode number f0ab rdmn r q channel minutes number (absolute) f0ac stat r/w 53cf94 (04); status register and destination id f0ad int r/w 53cf94 (05); interrupt register and time-out f0ae seqstp r/w 53cf94 (06); sequence step and synchronous transfer period f0af fifoflg r/w 53cf94 (07); fifo ?ags and synchronous offset f0b1 rdsc r q channel seconds (absolute) f0b2 rdfm r q channel frames (absolute) f0b3 wtpwm r/w pulse width modulator duty cycle select f0b4 config1 r/w 53cf94 (08); con?guration register number 1 f0b5 clock w 53cf94 (09); clock conversion factor f0b6 test w 53cf94 (0a); test mode f0b7 config2 r/w 53cf94 (0b); con?guration register number 2 f0b9 wtgctl w glic control registers (audio control) f0ba rdsw r drive control switches register f0bb fectl r/w front-end control register f0bc config3 r/w 53cf94 (0c); con?guration register number 3 f0bd config4 r/w 53cf94 (0d); con?guration register number 4 f0be tchigh r/w 53cf94 (0e); transfer count high and scsi id f0bf fifobtm w 53cf94 (0f); fifo bottom f0c0 brgsel r/w baud rate generator select register
1996 jun 19 46 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (sequoia) saa7385 f0c1 auswp r/w audio byte swap control f0c2 gpioctl r/w general purpose bits control register f0c3 rddstat r data status register f0c9 rdjmprs r option jumper register f0d8 fstest r/w frequency synthesizer test register f0e2 fefrmoff r/w front-end 8 lsbs; frame offset f0e3 fefrmoff r/w front-end 4 msbs; frame offset (bit 0 to bit 3) f0e4 fefrm# r/w front-end 8 lsbs of the frame f0e5 fefrm# r/w front-end 3 msbs of the frame (bit 0 to bit 2) f0e6 lstcmpfm r 8 lsbs; last complete frame number f0e7 lstcmpfm r 3 msbs; last complete frame number (bit 0 to bit 2) f0e8 scsioffs r/w scsi 8 lsbs; offset start (a and b) f0e9 scsioffs r/w scsi 4 msbs; offset start (bit 0 to bit 3) f0ea scsioffe r/w scsi 8 lsbs; offset end (a and b) f0eb scsioffe r/w scsi 4 msbs; offset end (bit 0 to bit 3) f0ec scsisfrm r/w scsi 8 lsbs; start transfer frame number f0ed scsisfrm r/w scsi 3 msbs; start frame number (bit 0 to bit 2) f0ee scsicfrm r/w scsi 8 lsbs; current frame number f0ef scsicfrm r/w scsi 3 msbs; current frame number (bit 0 to bit 2) f0f4 eccfrm# r/w ecc 8 lsbs; frame number (frame address) f0f5 eccfrm# r/w ecc 3 msbs; frame number (bit 0 to bit 2) f0f6 micfrm# r/w microcontroller 8 lsbs; frame number (frame address) f0f7 micfrm# r/w microcontroller 3 msbs; frame number (bit 0 to bit 2) f0f8 lastfrm r/w last frame number for storage 8 lsbs f0f9 lastfrm r/w last frame number 3 msbs (bit 0 to bit 2) f0fb intrmsk r/w interrupt mask register f0fc intrflg r/w interrupt ?ag register f0fd scsimod r/w scsi mode control f0fe dramsel r/w dram selection/test mode register. f0ff pagereg r/w 80c32 linear address page register address mnemonic read/write description
1996 jun 19 47 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (sequoia) saa7385 14 limiting values in accordance with the absolute maximum rating system (iec 134). 15 operating characteristics 15.1 i 2 s-bus timing; data mode v dd = 4.75 to 5.25 v; v ss =0v; t amb = - 10 to +70 c; unless otherwise speci?ed. note 1. the i 2 s-bus timing is directly related to the overspeed factor n in the normal operating mode. in the lock-to-disc mode n is replaced by the disc speed factor d. symbol parameter min. max. unit v dd digital supply voltage - 0.5 +7 v v i(max) maximum input voltage on any pin v ss - 0.5 v dd + 0.5 v v o output voltage on any output - 0.5 +7 v t stg storage temperature - 55 +150 c symbol parameter conditions min. typ. max. unit i 2 s-bus timing (single speed n); see fig.13 and note 1 c lock input : clab t cy output clock period sample rate = f s - 472.4/n - ns sample rate = 2 f s - 236.2/n - ns sample rate = 4 f s - 118.1/n - ns t ch clock high time sample rate = f s 166/n -- ns sample rate = 2f s 83/n -- ns sample rate = 4f s 42/n -- ns t cl clock low time sample rate = f s 166/n -- ns sample rate = 2f s 83/n -- ns sample rate = 4f s 42/n -- ns i nputs : daab, wsab and efab t su set-up time sample rate = f s 95/n -- ns sample rate = 2f s 48/n -- ns sample rate = 4f s 24/n -- ns t h hold time sample rate = f s 95/n -- ns sample rate = 2f s 48/n -- ns sample rate = 4f s 24/n -- ns
1996 jun 19 48 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (sequoia) saa7385 15.2 eiaj timing; audio mode v dd = 4.75 to 5.25 v; v ss =0v; t amb = - 10 to +70 c; unless otherwise speci?ed. note 1. the eiaj timing is directly related to the overspeed factor n in the normal operating mode. in the lock-to-disc mode n is replaced by the disc speed factor d. symbol parameter conditions min. typ. max. unit eiaj timing (single speed n); see fig.14 and note 1 c lock input : clab t cy output clock period sample rate = f s - 472.4/n - ns sample rate = 2 f s - 236.2/n - ns sample rate = 4 f s - 118.1/n - ns t ch clock high time sample rate = f s 166/n -- ns sample rate = 2f s 83/n -- ns sample rate = 4f s 42/n -- ns t cl clock low time sample rate = f s 166/n -- ns sample rate = 2f s 83/n -- ns sample rate = 4f s 42/n -- ns i nputs : daab, wsab and efab t su set-up time sample rate = f s 95/n -- ns sample rate = 2f s 48/n -- ns sample rate = 4f s 24/n -- ns t h hold time sample rate = f s 95/n -- ns sample rate = 2f s 48/n -- ns sample rate = 4f s 24/n -- ns
1996 jun 19 49 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (sequoia) saa7385 fig.13 i 2 s-bus timing diagram. handbook, full pagewidth 1 0 15 14 13 12 11 10 9 8 7654321 0 clab daab wsab efab (error flags) left left lsb valid right msb valid right lsb valid right mge399 0.8 v 0.8 v clab t h clock period t cy t cl t su t ch v dd - 0.8v v dd - 0.8 v daab wsab efab handbook, full pagewidth clab daab 10 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 wsab efab left right mge400 0.8 v 0.8 v clab t h clock period t cy t cl t su t ch v dd - 0.8v v dd - 0.8 v daab wsab efab fig.14 eiaj timing diagram.
1996 jun 19 50 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (sequoia) saa7385 15.3 r-w timing (see fig.15) the data from sub-code r-w may be read via the v4 pin from the cd-decoder and has a format similar to rs232. the sub-code synchronization word is formatted by a pause of 200 m s minimum. each sub-code byte starts with a logic 1 followed by seven bits (q to w). the gap between bytes is variable between 1.3 and 90 m s. 15.4 c-?ag timing (see fig.16) a 1-bit flag signal is input to the cflag pin. this signal shows the status of the error corrector and interpolator and is updated every frame. fig.15 sub-code formatting and timing from the v4 pin. handbook, full pagewidth w96 1 q1r1s1t1u1v1w1 1 200 m s min 11.3 m s 11.3 m s min 90 m s max mge401 fig.16 c-flag output timing. handbook, full pagewidth f1 f2 f3 f4 f5 f6 f7 11.3 m s 45.4 m s (nominal speed) mge402
1996 jun 19 51 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (sequoia) saa7385 15.5 s2b interface timing the s2b serial interface consists of four lines (see fig.17): transmit data (txd) receive data (rxd) data path ready to accept data; active low ( cpr) basic engine ready to accept data; active low ( spr). these are used for communication. txd and cpr for sending acknowledges and information data to the data path and rxd and spr for receiving commands and parameters from the data path. the data is transferred frame-wise and asynchronously. a data frame is proceeded by a start-bit (active low), followed by the actual data byte, and again followed by a parity bit (even parity), and a stop bit (active high), see fig.18. in total, eleven bits per frame are incorporated. the interface is full duplex, meaning data frames may be transmitted and received simultaneously. the bit-rate is selectable: 187.5 kbits/s with a 2.6% error 62.5 kbits/s with a 0.4% error 31.25 kbits/s with a 0.4% error. fig.17 s2b interface. handbook, halfpage mge403 rxd data path sequoia basic engine cpr txd spr txd cpr rxd spr fig.18 s2b timing. handbook, halfpage mge404 s0 txd 01234567ps1 cpr
1996 jun 19 52 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (sequoia) saa7385 15.6 scsi interface timing v dd = 4.75 to 5.25 v; v ss =0v; t amb = - 10 to +70 c; unless otherwise speci?ed. symbol parameter conditions min. max. unit target asynchronous send; see fig.19 t 1 data set-up time to req low 60 - ns t 2 ack low to req high - 40 ns t 3 data hold time from ack low fifo not empty 5 - ns t 4 ack high to req low data already set-up - 40 ns target asynchronous receive; see fig.20 t 1 ack low to req high - 40 ns t 2 ack high to req low fifo not full - 40 ns t 3 data set-up time to ack low 0 - ns t 4 data hold time from req high 0 - ns fast scsi-2 single-ended transfers (10 mbytes/s) t arget synchronous output ; see fig.21 t 1 req or ack assertion period 35 - ns t 2 req or ack negation period 35 - ns t 3 data set-up time to req or ack low 33 - ns t 4 data hold time from ack or req low 45 - ns t arget synchronous input ; see fig.22 t 1 req or ack assertion period 20 - ns t 2 req or ack negation period 20 - ns t 3 data set-up time to req or ack low 0 - ns t 4 data hold time from ack or req low 10 - ns fig.19 target asynchronous send signal transitions. handbook, full pagewidth mge407 t 1 t 3 t 2 t 4 sd7 to sd0 req ack
1996 jun 19 53 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (sequoia) saa7385 fig.20 target asynchronous receive signal transitions. handbook, full pagewidth t 4 mge408 t 3 t 1 t 2 sd7 to sd0 req ack fig.21 target synchronous output. handbook, full pagewidth mge409 t 3 t 4 t 1 t 2 sd7 to sd0 req/ack fig.22 target synchronous input. handbook, full pagewidth mge410 t 3 t 4 t 1 t 2 sd7 to sd0 req/ack
1996 jun 19 54 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (sequoia) saa7385 15.7 microprocessor interface v dd = 4.75 to 5.25 v; v ss =0v; t amb = - 10 to +70 c; unless otherwise speci?ed. symbol parameter min. max. unit program memory fetch timing; see fig.23 t avll address valid to ale low 15 - ns t llax address hold after ale low 35 - ns t llpl ale low to psen low 25 - ns t plph psen pulse width 80 - ns t pliv psen low to valid input instruction - 65 ns t pxix input instruction hold after psen 0 - ns t pxiz input instruction ?oat after psen - 30 ns t aviv address to valid input instruction - 130 ns t plaz psen low to address ?oat - 6ns fig.23 program code fetch cycle. handbook, full pagewidth mge411 la7 to la0 a15 to a8 t plph t aviv t pxiz t pliv t plaz t pxix t avll + t llpl t llax + t avll psen
1996 jun 19 55 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (sequoia) saa7385 15.8 dram interface (the saa7385 is designed to operate with standard 70 ns drams) v dd = 4.75 to 5.25 v; v ss =0v; t amb = - 10 to +70 c; unless otherwise speci?ed. symbol parameter min. max. unit dram interface timing; see figs 24 to 28 t acc;ca access time from column address - 35 ns t hca;ras column address hold time from ras 55 - ns t su;ca column address set-up time 0 - ns t su;ra row address set-up time 0 - ns t acc;cas access time from cas - 20 ns t h;ca column address hold time 15 - ns t w;cas cas pulse width 20 10000 ns t h;cas cas hold time (cbr refresh) 15 - ns t caslz cas to output in low impedance 3 - ns t pcas cas precharge time 10 - ns t acc;pcas access time from cas precharge - 40 ns t pcas;ras cas to ras precharge time 5 - ns t h;cas cas hold time 70 - ns t su;cas cas set-up time (cbr refresh) 5 - ns t wcasl write command to cas lead time 20 - ns t h;dat data input hold time 15 - ns t hdat;ras data input hold time from ras 55 - ns t su;dat data input set-up time 0 - ns t d;off output buffer turn off delay 3 20 ns t cy;fpr/w fast page mode read or write cycle time 40 - ns t cy;fpr-w fast page mode read-write cycle time note 1 - ns t acc;ras access time from ras - 70 ns t dras;ca ras to column address delay time 15 35 ns t h;ra row address hold time 10 - ns t w;ras ras pulse width 70 10000 ns t w;rasfp ras pulse width (fast page mode) 70 100000 ns t ca;rasl column address to ras lead time 35 - ns t cy;r/w random read or write cycle time 130 - ns t dras;cas ras to cas delay time 20 50 ns t su;r read command set-up time 0 - ns t hrr;cas read command hold time (referenced to cas) 0 - ns t ref refresh period - 32 ns t pras ras precharge time 50 - ns t pras;cas ras to cas precharge time 0 - ns t hr;ras read command hold time (referenced to ras) 0 - ns t h;ras ras hold time 20 - ns t cy;r-w read-write cycle time n/a (1) - ns
1996 jun 19 56 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (sequoia) saa7385 note 1. not applicable. t rasl;w write command to ras lead time 20 - ns t trans transition time (rise or fall) 3 50 ns t hw write command hold time 15 - ns t hw;ras write command hold time (referenced to ras) 55 - ns t su;we we command set-up time 0 - ns t w;w write command pulse width 15 - ns t h;we we hold time (cbr refresh) 10 - ns t su;we we set-up time (cbr refresh) 10 - ns symbol parameter min. max. unit fig.24 dram read cycle. handbook, full pagewidth mge412 t pras t w;ras t cy;r/w t pcas;ras t dras;cas t w;cas t h;ras t h;cas t su;ra t h;ra t su;ca t dras;ca t hca;ras t ca;rasl t h;ca row column row t acc;ca t acc;ras t acc;cas t caslz t d;off address data cas ras
1996 jun 19 57 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (sequoia) saa7385 fig.25 dram early write cycle. handbook, full pagewidth mge413 t pras t w;ras t cy;r/w t pcas;ras t dras;cas t w;cas t h;ras t h;cas t su;ra t h;ra t su;ca t dras;ca t hca;ras t ca;rasl t h;ca row column row t hdat;ras t su;dat t h;dat address data cas ras
1996 jun 19 58 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (sequoia) saa7385 a ndbook, full pagewidth mge414 t w;rasfp t pcas;ras t dras;cas t w;cas t cy;fpr / w t pcas t pcas t w;cas t h;ras t w;cas t h;cas t su;ra t su;ca t h;ra t dras;ca t hca;ras row column column column t h;ca t d;off t caslz t acc;cas t acc;pcas t acc;ca t d;off t caslz t acc;cas t acc;pcas t acc;ca t d;off t caslz t acc;cas t acc;pcas t acc;ca t h;ca t su;ca t ca;rasl t su;ca t h;ca address data cas ras fig.26 fast page mode dram read cycle.
1996 jun 19 59 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (sequoia) saa7385 a ndbook, full pagewidth mge415 t w;ras t pcas;ras t dras;cas t w;cas t cy;fpr / w t pcas t pcas t w;cas t h;ras t hdat;ras t w;cas t h;cas t su;ra t su;dat t su;dat t su;ca t h;ra t dras;ca t hca;ras row column column column t h;ca t h;dat t su;dat t h;dat t h;dat t h;ca t su;ca t ca;rasl t su;ca t h;ca address data cas ras fig.27 fast page mode dram write cycle.
1996 jun 19 60 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (sequoia) saa7385 fig.28 dram refresh cycle. handbook, full pagewidth mge416 t w;ras t pras t cy;r/w t pcas;ras t pras;cas t su;ra t h;ra address row row cas ras
1996 jun 19 61 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (sequoia) saa7385 16 package outline unit a 1 a 2 a 3 b p ce (1) eh e ll p y w v q references outline version european projection issue date iec jedec eiaj mm 0.25 0.25 3.05 2.55 0.27 0.17 0.20 0.09 14.0 20.0 0.50 17.2 7 0 o o 0.08 0.10 0.20 1.60 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.95 0.65 sot387-2 96-03-14 d (1) h d 23.2 e q e a 1 a l p detail x l (a ) 3 b 38 b p e h a 2 d a e v m a 1 128 103 102 65 64 39 pin 1 index y b p d h v m b w m w m 0 5 10 mm scale c sqfp128: plastic shrink quad flat package; 128 leads (lead length 1.6 mm); body 14 x 20 x 2.8 mm sot387-2 a max. min. 3.40 x
1996 jun 19 62 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (sequoia) saa7385 17 soldering 17.1 introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). 17.2 re?ow soldering reflow soldering techniques are suitable for all qfp packages. the choice of heating method may be influenced by larger plastic qfp packages (44 leads, or more). if infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. for more information, refer to the drypack chapter in our quality reference handbook (order code 9397 750 00192). reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several techniques exist for reflowing; for example, thermal conduction by heated belt. dwell times vary between 50 and 300 seconds depending on heating method. typical reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheating duration: 45 minutes at 45 c. 17.3 wave soldering wave soldering is not recommended for qfp packages. this is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. if wave soldering cannot be avoided, the following conditions must be observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. even with these conditions, do not consider wave soldering the following packages: qfp52 (sot379-1), qfp100 (sot317-1), qfp100 (sot317-2), qfp100 (sot382-1) or qfp160 (sot322-1). during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 17.4 repairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
1996 jun 19 63 philips semiconductors preliminary speci?cation error correction and host interface ic for cd-rom (sequoia) saa7385 18 definitions 19 life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation.
internet: http://www.semiconductors.philips.com/ps/ (1) address content source june 19, 1996 philips semiconductors C a worldwide company ? philips electronics n.v. 1996 sca49 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 83749, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland: ul. lukiska 10, pl 04-123 warszawa, tel. +48 22 612 2831, fax. +48 22 612 2327 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 926 5361, fax. +7 095 564 8323 singapore: lorong 1, toa payoh, singapore 1231, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 7430 johannesburg 2000, tel. +27 11 470 5911, fax. +27 11 470 5494 south america: rua do rocio 220 - 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